Capacitor and method for fabricationg the same, and semiconductor device and method for fabricating the same

ABSTRACT

The semiconductor device comprises a device isolation region  14  formed in a semiconductor substrate  10 , a lower electrode  16  formed in a device region  12  defined by the device isolation region and formed of an impurity diffused layer, a dielectric film  18  of a thermal oxide film formed on the lower electrode, an upper electrode  20  formed on the dielectric film, an insulation layer  26  formed on the semiconductor substrate, covering the upper electrode, a first conductor plug  30   a  buried in a first contact hole  28   a  formed down to the lower electrode, and a second conductor plug  30   b  buried in a second contact hole  28   b  formed down to the upper electrode, the upper electrode being not formed in the device isolation region. The upper electrode  20  is not formed in the device isolation region  14 , whereby the short-circuit between the upper electrode  20  and the lower electrode  16  in the cavity can be prevented. Thus, a capacitor of high reliability can be provided.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. application Ser. No.10/924,956, filed on Aug. 25, 2004, which is based upon and claimspriority of Japanese Patent Application No. 2004-73018, filed on Mar.15, 2004, the contents being incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a capacitor and a method forfabricating the capacitor, and a semiconductor device including thecapacitor and a method for fabricating the semiconductor device.

Recently, semiconductor devices including semiconductor elements, suchas transistors, etc., and capacitors formed on one and the samesubstrates are noted.

For example, a capacitor comprising a lower electrode of a heavily dopedimpurity diffused layer buried in a semiconductor substrate, adielectric film formed by thermally oxidizing the surface of thesemiconductor substrate, and an upper electrode formed on the dielectricfilm is known.

A semiconductor device having semiconductor elements and the capacitorsformed on one and the same substrate can remove noises by the capacitorswithout leading the interconnections outside the semiconductor deviceand accordingly can realize more stable operation.

Following references disclose the background art of the presentinvention.

[Patent Reference 1]

Specification of Japanese Patent Application Unexamined Publication No.2003-218224

[Patent Reference 2]

Specification of Japanese Patent Application Unexamined Publication No.2003-60097

[Patent Reference 3]

Specification of Japanese Patent No. 2826149

However, such capacitors do not have high reliability.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a capacitor of highreliability and a method for fabricating the capacitor, a semiconductordevice using the capacitor and a method for fabricating thesemiconductor device.

According to one aspect of the present invention, there is provided acapacitor comprising: a device isolation region formed on asemiconductor substrate; a lower electrode formed in a device regiondefined by the device isolation region, and formed of an impuritydiffused layer; a dielectric film formed of a thermal oxide film formedover the lower electrode; an upper electrode formed over the dielectricfilm; an insulation layer formed over the semiconductor substrate,covering the upper electrode; a first conductor plug buried in a firstcontact hole which is down to the lower electrode; and a secondconductor plug buried in a second contact hole which is down to theupper electrode, the upper electrode being not formed over the deviceisolation region.

According to another aspect of the present invention, there is provideda semiconductor device comprising: a device isolation region formed in asemiconductor substrate; a transistor including a gate insulation filmformed of a thermal oxide film formed in a first device region definedby the device isolation region, and a gate electrode formed over thegate insulation film and the device isolation region; a capacitorincluding a lower electrode formed in a second device region defined bythe device isolation region, a dielectric film formed over the lowerelectrode and formed of a thermal oxide film thicker than the gateinsulation film; and an upper electrode formed over the dielectric film;an insulation film formed over the semiconductor substrate, covering thetransistor and the capacitor; a first conductor plug buried in a firstcontact hole which is down to the lower electrode; a second conductorplug buried in a second contact hole which is down to the upperelectrode; and a third conductor plug buried in a third contact holewhich is down to the gate electrode, the upper electrode of thecapacitor being not formed over the device isolation region.

According to further another aspect of the present invention, there isprovided a method for fabricating a capacitor comprising the steps of:forming a device isolation region in a semiconductor substrate; forminga sacrifice oxidation film on the surface of the device region definedby the device isolation region; implanting an impurity in a regioncontaining the device region to form a lower electrode of an impuritydiffused layer: etching off the sacrifice oxidation film; forming adielectric film on the surface of the impurity diffused layer by thermaloxidation; forming an upper electrode over the dielectric film; formingan insulation layer, covering the upper electrode; etching theinsulation layer to form a first contact hole down to the lowerelectrode and a second contact hole down to the upper electrode; andburying the first conductor plug in the first contact hole and buryingthe second conductor plug in the second contact hole, in the step offorming the upper electrode, the upper electrode is not formed over thedevice isolation region.

According to further another aspect of the present invention, there isprovided a method for fabricating a semiconductor device comprising thesteps of: forming a device isolation region in a semiconductorsubstrate; forming a sacrifice oxidation film on the surface of a deviceregion defined by the device isolation region and the surface of anotherdevice region defined by the device isolation region; implanting animpurity into a region containing said another device region to form alower electrode of a impurity diffused layer; etching off the sacrificeoxidation film; forming a gate insulation film on the surface of thedevice region, and a dielectric film thicker than the gate insulationfilm on the surface of the impurity diffused layer, by thermaloxidation; forming a gate electrode over the gate insulation film andthe device isolation region, and an upper electrode over the dielectricfilm; forming an insulation layer, covering the gate electrode and theupper electrode; etching the insulation layer to form a first contacthole down to the lower electrode, a second contact hole down to thefirst electrode and a third contact hole down to the gate electrode; andburying a first conductor plug, a second conductor plug and a thirdconductor plug respectively in the first contact hole, the secondcontact hole and the third contact hole, in the step of forming theupper electrode, the upper electrode being not formed over the deviceisolation region.

According to the present invention, the upper electrode is not formed inthe device isolation region, whereby the short-circuit between the upperelectrode and the lower electrode in the cavity can be prevented. Thus,the present invention can provide a capacitor of high reliability.

The present invention can provide a capacitor of high reliability, andaccordingly can provide a semiconductor device of high reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are a sectional view and a plane view of the capacitoraccording to a first embodiment of the present invention.

FIG. 2 is a graph of relationships between the density of contacts andthe yield.

FIG. 3 is a graph of the failure rate of the capacitor according to thefirst embodiment of the present invention.

FIGS. 4A to 4C are sectional views of the capacitor according to thefirst embodiment of the present invention in the steps of the method forfabricating the capacitor, which illustrate the method (Part 1).

FIGS. 5A to 5C are sectional views of the capacitor according to thefirst embodiment of the present invention in the steps of the method forfabricating the capacitor, which illustrate the method (Part 2).

FIGS. 6A to 6C are sectional views of the capacitor according to thefirst embodiment of the present invention in the steps of the method forfabricating the capacitor, which illustrate the method (Part 3).

FIGS. 7A and 7B are a sectional view and a plane view of thesemiconductor device according to a second embodiment of the presentinvention.

FIGS. 8A and 8B are sectional views of the semiconductor device in thesteps of the semiconductor device fabricating method according to thesecond embodiment of the present invention (Part 1).

FIGS. 9A and 9B are sectional views of the semiconductor device in thesteps of the semiconductor device fabricating method according to thesecond embodiment of the present invention (Part 2).

FIGS. 10A and 10B are sectional views of the semiconductor device in thesteps of the semiconductor device fabricating method according to thesecond embodiment of the present invention (Part 3).

FIGS. 11A and 11B are sectional views of the semiconductor device in thesteps of the semiconductor device fabricating method according to thesecond embodiment of the present invention (Part 4).

FIGS. 12A and 12B are diagrammatic views of the proposed capacitor.

FIG. 13 is a graph of the failure rate of the proposed capacitor.

FIGS. 14A to 14C are sectional views of the proposed capacitor in thesteps of the method for fabricating the capacitor, which illustrate themethod (Part 1).

FIGS. 15A and 15B are sectional views of the proposed capacitor in thesteps of the method for fabricating the capacitor, which illustrate themethod (Part 2).

DETAILED DESCRIPTION OF THE INVENTION Principle of the Present Invention

A proposed capacitor will be explained with reference to FIGS. 12A and12B. FIGS. 12A and 12B are diagrammatic views of the proposed capacitor.FIG. 12A is a sectional view of the proposed capacitor. FIG. 12B is aplane view of the proposed capacitor.

As illustrated in FIGS. 12A and 12B, a device isolation region 114 isformed in a silicon substrate 110. In a device region 112 defined by thedevice isolation region 114, a lower electrode 116 of a heavily dopedimpurity diffused layer is formed.

A dielectric film 118 is formed on the lower electrode 116. Thedielectric film 118 is formed by thermally oxidizing the surface of theheavily doped impurity diffused layer 116. When the heavily dopedimpurity diffused layer 116 is thermally oxidized, the phenomena thatthe oxidation advances due to the presence of the dopant impurity. Thisphenomena is called accelerating oxidation. Because of the acceleratingoxidation taking place when the dielectric film 118 is formed, thedielectric film 118 is formed relatively thick.

An upper electrode 120 of polysilicon is formed on the dielectric film118. The upper electrode 120 is formed not only over the device region112 but also over the device isolation region 114. The lower electrode116, the dielectric film 118 and the upper electrode 120 form acapacitor 122.

An inter-layer insulation film 126 is formed on a silicon substrate 110with the upper electrode 120, etc. formed on. In the inter-layerinsulation film 126, a contact hole 128 b and a contact hole 128 a areformed respectively down to the upper electrode 120 and down to thelower electrode 116. Conductor plugs 130 a, 130 b are buriedrespectively in the contact holes 128 a, 128 b.

Thus, the proposed capacitor 132 is constituted.

In the proposed capacitor, an impurity is heavily doped in the lowerelectrode 116, which makes it difficult for the lower electrode 116 tobe depleted when a voltage is applied to the upper electrode 120.Because of the dielectric film 118 which is formed relatively thick bythe accelerating oxidation, the electric field between the lowerelectrode 116 and the upper electrode 120 is relatively small. Theproposed capacitor 132, in which the lower electrode 116 is not easilydepleted, and the electric field between the lower electrode 116 and theupper electrode 120 is relatively small, can have relatively low voltagedependency.

However, the reliability of the proposed capacitor is not so high.

FIG. 13 is a graph of the failure rate of the proposed capacitor. Thegraph is shown in Weibull plot. On the horizontal axis, the total chargeinjection amount QBD required until the dielectric breakdown takesplace. The failure rates ln(1/1−F(t)) are taken on the vertical axis.F(t) is a failure rate distribution function.

As seen in FIG. 13, the dielectric breakdown took place below the totalcharge injection amount of 1 C/cm². The total charge injection amountQBD required until the dielectric breakdown took place are largelydispersed.

Thus, the reliability of the proposed capacitor is not so high.

The inventors of the present application have investigated causes forthe low reliability of the proposed capacitor.

FIGS. 14A to 15B are sectional views of the proposed capacitor in thesteps of the method for fabricating the proposed capacitor, whichillustrate the method.

First, as illustrated in FIG. 14A, the device isolation region 114 isformed in the silicon substrate 110 by, e.g., STI. The device isolationregion 114 defines the device region 112. Then, a sacrifice oxidationfilm 134 is formed on the surface of the semiconductor substrate 110.

Then, a photoresist film 136 is formed on the entire surface. Next, anopening 138 for exposing the device region 112 is formed in thephotoresist film 136. Then, with the photoresist film 136 as the mask adopant impurity is heavily implanted. Thus, the lower electrode 116 ofthe heavily doped impurity diffused layer is formed (see FIG. 14B).

Next, the sacrifice oxidation film 134 is etched off by using, e.g.,hydrofluoric acid. In the device isolation region 114 nearer to thedevice region 112, the dopant impurity is more heavily implanted, andthe etching advances at higher rate. Thus, a cavity 115 is formed in thedevice isolation region 114 nearer to the device region 112 (see FIG.14C).

Then, as illustrated in FIG. 15A, the dielectric film 118 of a siliconoxide film is formed on the surface of the silicon substrate 110 bythermal oxidation. The dielectric film 118, which is formed by thermallyoxidizing the heavily doped impurity diffused layer, is formed of thesilicon oxide film 118 of a relatively thick film thickness due to theaccelerating oxidation caused by the presence of the dopant impurity.The accelerating oxidation is oxidation which advances at high rates dueto the presence of an impurity. The accelerating oxidation does notoccur in the region where the dopant impurity is not been heavilyimplanted, and the film thickness of the silicon oxide film there isrelatively small. The accelerating oxidation occurs in the region wherethe dopant impurity is heavily implanted, and the film thickness of thesilicon oxide film there is relatively large.

Next, the upper electrode 120 of a polysilicon film with a dopantimpurity implanted is formed.

Then, the inter-layer insulation film 126 is formed on the entiresurface.

Then, the opening 128 b and the opening 128 a are formed in theinter-layer insulation film 126 respectively down to the upper electrode120 and the lower electrode 116 by photolithography.

Then, the conductor plugs 130 a, 130 b are buried respectively in theopenings 128 a, 128 b.

Thus, the capacitor 132 including the lower electrode 116, thedielectric film 118 and the upper electrode 120 is formed (see FIG.15B).

As illustrated in FIG. 15B, the film thickness of the dielectric film118 in the cavity 115 is very small. Furthermore, the dielectric film118, which is formed by oxidizing the heavily doped impurity diffusedlayer 118, will not have good film quality. Accordingly, in the proposedcapacitor 132, the dielectric breakdown occurs in the cavity 115, whichwill be a cause for the low reliability.

Based on the above-described results of the investigation, the inventorsof the present application has had an idea that the absence of the upperelectrode 120 in the cavity 115 prevents the short-circuit between theupper electrode 120 and the lower electrode 116, which improve thereliability of the capacitor.

A First Embodiment

The capacitor according to a first embodiment of the present inventionand a method for fabricating the capacitor will be explained withreference to FIGS. 1A to 6C. FIG. 1A is a sectional view of thecapacitor according to the present embodiment. FIG. 1B is a plane viewof the capacitor according to the present embodiment.

(The Capacitor)

First, the capacitor according to the present embodiment will beexplained with reference to FIGS. 1A and 1B.

As illustrated in FIGS. 1A and 1B, a device isolation region 14 fordefining a device region 12 is formed in a semiconductor substrate 10.The semiconductor substrate 10 is, e.g., a p type semiconductorsubstrate, more specifically a p type silicon substrate. The deviceisolation region 14 is formed by, e.g., STI (Shallow Trench Isolation).

A cavity 15 is formed in the device isolation region 14 near the deviceregion 12.

A P type well (not illustrated) is formed in the device region 12.

In the device region 12, a lower electrode 16 of, e.g., an N⁺ typeheavily doped impurity diffused layer is formed. The dopant impurity is,e.g., arsenic (As⁺). The lower electrode 16 is formed in contact withthe device isolation region 14. The peak value of the concentration ofthe dopant impurity in the lower electrode 16 is, e.g., 1×10²⁰ cm^(˜3)or more. The impurity concentration of the lower electrode 16 is set tobe so high so as to prevent the depletion of the lower electrode 16.

A dielectric film (capacitor dielectric film) 18 is formed on the lowerelectrode 16. The dielectric film 18 is formed by thermally oxidizingthe N⁺ type heavily doped impurity diffused layer 16. The oxidation ofthe region 16 where the dopant impurity is heavily implanted advances ata higher rate than the oxidation of the region where the dopant impurityis not heavily implanted. The oxidation of the former advances at ahigher rate because the dopant impurity advances the oxidation.Accordingly, when the region 16 where the dopant impurity is heavilyimplanted and the region where the dopant impurity is not heavilyimplanted are thermally oxidized concurrently, the film thickness of theoxide film 18 formed on the surface of the region 16 is larger than thefilm thickness of the oxide film formed on the surface of the regionwhere the dopant impurity is not heavily implanted. Under conditions forforming the oxide film of, e.g., an about 7 nm-thickness on the surfaceof the silicon substrate where the dopant impurity is not heavilyimplanted, the oxide film of, e.g., an about 14 nm-thickness is formedon the surface of the silicon substrate where the dopant impurity isheavily implanted. Such phenomena is called an accelerating oxidation,and the oxide film thus formed is called an accelerating oxide film.With the peak value of the concentration of the dopant impurity in thelower electrode 16 being, e.g., 1×10²⁰ cm⁻³ or more, the dielectric film18 of a sufficient thickness can be formed by the acceleratingoxidation.

An upper electrode 20 is formed on the dielectric film 18 of theaccelerating oxide film. The upper electrode 20 is, e.g., a polysiliconfilm with an impurity implanted (doped polysilicon film). The upperelectrode 20 is not formed over the device isolation region. In thepresent embodiment, the upper electrode 20 is not formed over the deviceisolation region 14 so as to prevent the short-circuit between the lowerelectrode 16 and the upper electrode 20 in the cavity 15.

The lower electrode 16, the dielectric film 18 and the upper electrode20 form a capacitor 22.

An etching stopper film 24 is formed on the semiconductor substrate 10with the capacitor 22 formed on. The etching stopper film 24 is, e.g.,silicon nitride film.

An inter-layer insulation film 26 is formed on the semiconductorsubstrate 10 with the etching stopper film 24 formed on. The inter-layerinsulation film 26, e.g., a silicon oxide film.

In the inter-layer insulation film 26 and the etching stopper film 24, acontact hole 28 a and a contact hole 28 b are formed respectively downto the lower electrode 16 and the upper electrode 20.

Conductor plugs 30 a, 30 b are buried respectively in the contact holes28 a, 28 b. The material of the conductor plugs 30 a, 30 b is tungsten.

FIG. 2 is a graph of relationships between the density of the contactsand the yield. On the horizontal axis, the densities of the contacts bymeans of the conductor plug 30 a are taken. On the vertical axis, theyields are taken. As seen in FIG. 2, preferably, the density of thecontacts by means of the conductor plugs 30 a is set, e.g., at 0.01contacts/μm² or less.

The capacitor 32 according to the present embodiment is thusconstituted.

(Evaluation Result)

The result of evaluating the capacitor according to the presentembodiment will be explained with reference to FIG. 3. FIG. 3 is a graphof the failure rate of the capacitor according to the presentembodiment. The graph is shown in Weibull plot. On the horizontal axistotal charge injection amount QBD (C/cm²) required until the dielectricbreakdown took place. On the vertical axis, the failure ratesln(1/1−F(t)) are taken. The F(t) is the failure distribution function.

As seen in FIG. 3, the total charge injection amount QBD required tocause the dielectric breakdown is above about 10 C/cm². The dispersionof the total charge injection amount QBD required to cause thedielectric breakdowns are very small. Based on this, it can be seen thatthe capacitor according to the present embodiment can have highreliability.

(The Method for Fabricating the Capacitor)

Next, the capacitor according to the present embodiment will beexplained with reference to FIGS. 4A to 6C. FIGS. 4A to 6C are sectionalviews of the capacitor according to the present embodiment in the stepsof the method for fabricating the capacitor, which illustrate themethod.

As illustrated in FIG. 4A, the device isolation region 14 is formed onthe semiconductor substrate 10 by, e.g., STI. The semiconductorsubstrate 10 is, e.g., a silicon substrate. The device isolation region14 defines the device region 12.

Next, the sacrifice oxidation film 34 is formed on the surface of thesemiconductor substrate 10 by thermal oxidation.

Next, a dopant impurity is implanted into the device region 12 tothereby form, e.g., the P type well (not illustrated) in thesemiconductor substrate 10.

Then, a photoresist film 36 is formed on the entire surface by, e.g.,spin coating.

Next, as illustrated in FIG. 4B, the opening 38 is formed in thephotoresist film 36 by photolithography. The opening 38 is formed,exposing not only the device region 12 but also the device isolationregion 14 around the device region 12.

Then, with the photoresist film 36 as the mask, an N type dopantimpurity is heavily implanted in the device region 12 by, e.g., ionimplantation. The dopant impurity is implanted also into the deviceisolation region 14 around the device region 12. The dopant impurity isimplanted into the semiconductor substrate 10 through the sacrificeoxidation film 34. The dopant impurity is, e.g. arsenic (As⁺).Conditions for the ion implantation are, e.g., a 60 keV accelerationvoltage and a 1.0×10¹⁵ cm⁻² dose. The lower electrode 16 of the heavilydoped impurity diffused layer is thus formed in the device region 12.

Next, as illustrated in FIG. 4C, the sacrifice oxidation film 34 on thesurface of the semiconductor substrate 10 is etched off by using, e.g.,a hydrofluoric acid solution. When the sacrifice oxidation film 34 isremoved, the device isolation region 14 around the device region 12,where the dopant impurity is heavily implanted, is etched more deeply.The cavity 15 is thus formed in the device isolation region 14 aroundthe device region 12.

Next, as illustrated in FIG. 5A, the dielectric film 18 of a siliconoxide film 18 is formed by thermal oxidation. The film thickness of thedielectric film 18 is about 14 nm. The temperature of the inside of thefilm forming chamber for forming the dielectric film 18 is about 800° C.The atmosphere inside the film forming chamber is an atmosphere mixingsteam and DCE (Dichloroethane). The region 16 where the dopant impurityis heavily implanted is thermally oxidized to thereby form thedielectric film 18, in which the presence of the dopant impurity causesthe accelerating oxidation, and the film thickness of the dielectricfilm 18 becomes relatively large.

Next, a polysilicon film with a dopant impurity implanted in is formedby, e.g., CVD. A condition for forming the polysilicon film is, e.g.,about 620° C.

Then, the polysilicon film is patterned by photolithography. Thepolysilicon film is pattered not be present over the device isolationregion 14. The upper electrode 20 is thus formed of the polysilicon film(see FIG. 5B).

Then, as illustrated in FIG. 5C, a silicon nitride film 24 is formed onthe entire surface by, e.g., plasma-enhanced CVD. The film thickness ofthe silicon nitride film 24 is, e.g., about 50 nm. The silicon nitridefilm 24 functions as an etching stopper film.

Next, the inter-layer insulation film 26 of, e.g., a silicon oxide filmis formed on the entire surface by, e.g., CVD. The film thickness of theinter-layer insulation film 26 is, e.g., about 950 nm.

Then, the surface of the inter-layer insulation film 26 is polished. Thesurface of the inter-layer insulation film 26 is thus flattened.

Then, as illustrated in FIG. 6A, with the silicon nitride film 24 as theetching stopper, the contact holes 28 a, 28 b are formed in theinter-layer insulation film 26 by photolithography. Dry etching is usedto form the contact holes 28 a, 28 b in the inter-layer insulation film26. The etching gas is, e.g., a CF-based etching gas. The etching systemis, e.g., a high density plasma etching system. The inter-layerinsulation film 26 is etched with a high selectivity ratio to thesilicon nitride film 24, whereby the etching can be stopped by thesilicon nitride film 24 without failure.

Next, as illustrated in FIG. 6B, the silicon nitride film 24, etc.exposed in the contact holes 28 a, 28 b are etched. The contact hole 28b and the contact hole 28 a are thus formed respectively down to theupper electrode 20 and the lower electrode 16.

Then, a titanium film (not illustrated) and a titanium nitride film (notillustrated) are sequentially formed by, e.g., CVD. A barrier metal film(not illustrated) is thus formed of the titanium film and titaniumnitride film. The film thickness of the titanium film is, e.g., about 10nm. The film thickness of the titanium nitride film is, e.g., about 20nm.

Then, a tungsten film is formed by, e.g., CVD. The film thickness of thetungsten film is, e.g., about 300 nm.

Next, the tungsten film and the barrier metal film are polished by,e.g., CMP until the surface of the inter-layer insulation film 26 isexposed. Thus, the conductor plugs (contact plugs) of the tungsten areburied in the contact holes 28 a, 28 b (see FIG. 6C).

Thus, the semiconductor device according to the present embodiment isfabricated.

One main characteristics of the capacitor according to the presentembodiment is that the lower electrode 16 is formed in contact with thedevice isolation region 14, while the upper electrode 20 is not formedover the device isolation region 14.

According to the present embodiment, the upper electrode 20 is notformed over the device isolation region 14, which can prevent theshort-circuit between the upper electrode 20 and the lower electrode 16in the cavity 15 of the device isolation region 14. The capacitoraccording to the present embodiment can have high reliability.

Another main characteristic of the capacitor according to the presentembodiment is that the etching stopper film 24 is formed, covering thecapacitor 22.

In the first step of the etching for forming the contact holes 28 a, 28b, the inter-layer insulation film 26 is etched with the silicon nitridefilm 24 as the etching stopper film and with a high selectivity, wherebythe silicon nitride film 24 can stop the etching without failure. In thesecond step of the etching for forming the contact holes 28 a, 28 b, thesilicon nitride film 24, etc. to be removed are so thin that the etchingrate can be very easily controlled. Thus, according to the presentembodiment, the lower electrode 16 and the upper electrode 20 areprevented from being damaged. Accordingly, the capacitor according tothe present embodiment can have higher reliability.

The technique of the invention of the present application that theshort-circuit between the upper electrode and the lower electrode in thecavity of the device isolation region can be prevented is neitherdisclosed nor suggested in any one of Patent Reference 1 to 3.

The technique of the invention of the present application that the upperelectrode and the lower electrode are prevented from being damaged byusing the etching stopper film whereby improve the reliability of thecapacitor is neither disclosed nor suggested in any one of PatentReference 1 to 3.

A Second Embodiment

The semiconductor device according to a second embodiment of the presentinvention and the method for fabricating the semiconductor device willbe explained with reference to FIGS. 7A to 11B. FIG. 7A is a sectionalview of the semiconductor device according to the present embodiment.FIG. 7B is a plane view of the semiconductor device according to thepresent embodiment. The same members of the present embodiment as thoseof the capacitor according to the first embodiment and the method forfabricating the capacitor illustrated in FIGS. 1A to 6C are representedby the same reference numbers not to repeat or to simplify theirexplanation.

(The Semiconductor Device)

The semiconductor device according to the present embodiment ischaracterized mainly in that semiconductor elements, such as atransistor 40, etc. and the capacitor 32 according to the firstembodiment are formed on one and the same semiconductor substrate 10.

As illustrated in FIGS. 7A and 7B, a gate insulation film 18 a is formedon the surface of a device region 12 a defined by the device isolationregion 14. The film thickness of the gate insulation film 18 a issmaller than the film thickness of the dielectric film 18. The filmthickness of the gate insulation film 18 a is, e.g., 7 nm. The gateinsulation film 18 a of the transistor 40 is formed thinner than thedielectric film 18 of the capacitor 32, because the device region 12 awhere a dopant impurity is not heavily implanted in the device region 12a for the transistor 40 to be formed in, and the accelerating diffusiondoes to take place. The gate insulation film 18 a formed in the deviceregion 12 a without a heavily dopant implantation has good quality.

A gate electrode 20 a is formed over the device region 12 a and thedevice isolation region 14. The gate electrode 20 a is formed of, e.g.,polysilicon film with a dopant impurity implanted in. The upperelectrode of the capacitor 32 and the gate electrode 20 a of thetransistor 40 are formed of the one and the same conducting film.

A sidewall insulation film 42 is formed on the side wall of the gateelectrode 20 a. The sidewall insulation film 42 is formed of, e.g., asilicon oxide film.

A source/drain diffused layer (not illustrated) is formed in the deviceregion 12 a on both side of the gate electrode 20 a with the sidewallinsulation film 42 formed on.

The etching stopper film 24 is formed on the transistor 40 and thecapacitor 32.

The inter-layer insulation film 26 is formed on the etching stopper film24.

A contact hole 28 c is formed in the inter-layer insulation film 26 andthe etching stopper film 24 down to the gate electrode 20 a.

A conductor plug 30 c is buried in the contact hole 28 c.

Thus, the semiconductor device according to the present embodiment isfabricated.

(The Method for Fabricating the Semiconductor Device)

Next, the method for fabricating the semiconductor device according tothe present embodiment will be explained with reference to FIGS. 8A to11B. FIGS. 8A to 11B are sectional views of the semiconductor deviceaccording to the present embodiment in the steps of the method forfabricating the semiconductor device, which illustrate the method.

First, as illustrated in FIG. 8A, the device isolation region 14 fordefining the device regions 12, 12 a is formed by, e.g., STI. Thus, thedevice region 12 for the capacitor 32 to be formed in, and the deviceregion 12 for the transistor 40 to be formed in are defined by thedevice isolation region 14.

Next, the sacrifice oxidation film 34 is formed on the surface of thesemiconductor substrate 10 by thermal oxidation.

Next, a dopant impurity is implanted in the device regions 12, 12 a toform, e.g., P type wells (not illustrated) in the semiconductorsubstrate 10.

Next, as illustrated in FIG. 8B, a photoresist film 36 is formed on theentire surface by spin coating.

Next, the opening 38 is formed in the photoresist film 36 byphotolithography. The opening 38 is formed, exposing not only the deviceregion 12 but also the device isolation region 14 around the deviceregion 12.

Next, with the photoresist film 36 as the mask, a dopant impurity isimplanted in the device region 12 by, e.g., ion implantation. At thistime, the dopant impurity is implanted also in the device isolationregion 14 around the device region 12. The dopant impurity is implantedinto the semiconductor substrate 10 through the sacrifice oxidation film34. The dopant impurity is, e.g., arsenic (As⁺). Conditions for the ionimplantation are, e.g., 60 keV acceleration voltage and 1.0×10¹⁵ cm⁻²dose.

Then, the sacrifice oxidation film 34 on the surface of thesemiconductor substrate 10 is etched off by using, e.g., a hydrofluoricacid solution.

Then, as illustrated in FIG. 9A, the silicon oxide film 18, 18 a areformed on the surface of the semiconductor substrate 10 by thermaloxidation. The silicon oxide film 18 formed in the device region 12 isto be the dielectric film of the capacitor 32. The silicon oxide film 18a formed in the device region 12 a is to the gate insulation film 18 aof the transistor 40. The dielectric film 18 and the gate insulationfilm 18 a are formed at an about 800° C. internal temperature of thefilm forming chamber. The atmosphere in the film forming chamber is anatmosphere mixing steam and DCE (Dichloroethane). In the device region12, the dielectric film 18, which is formed by thermally oxidizing thesurface of the heavily doped impurity diffused layer 16, has arelatively large film thickness d₁ due to the accelerating oxidationcaused by the presence of the dopant impurity. On the other hand, in thedevice region 12 a, where the dopant impurity is not heavily implanted,the accelerating oxidation does not take place, and the film thicknessd₂ of the gate insulation film 18 a is relatively small. The filmthickness d₁ of the dielectric film 18 is about 14 nm, and the filmthickness d₂ of the gate insulation film 18 a is, e.g., 7 nm.

Then, a polysilicon film is formed by, e.g., CVD. A condition forforming the polysilicon film is, e.g., about 620° C.

Next, the polysilicon film is patterned by photolithography to form theupper electrode 18 and the gate electrode 18 a. The polysilicon film ispatterned for the upper electrode 18 not to present over the deviceisolation region 14. On the other hand, as for the gate electrode 18 a,the polysilicon film is patterned for the gate electrode 18 a to bepositioned over the device region 12 and the device isolation region 14(see FIG. 9B). The cavity 15 is not formed in the device isolationregion 14 near the device isolation region 12 a, whereby the gateelectrode 18 a formed over the device isolation region 14 can beprevented from short-circuiting with the device region 12 a.

Next, as illustrated in FIG. 10A, the silicon nitride film 24 is formedon the entire surface by, e.g., plasma-enhanced CVD. The film thicknessof the silicon nitride film 24 is, e.g., about 50 nm. The siliconnitride film 24 functions as the etching stopper film.

Then, the inter-layer insulation film 26 is formed on the entire surfaceby, e.g., CVD. The film thickness of the inter-layer insulation film 26is, e.g., about 950 nm.

Next, the surface of the inter-layer insulation film 26 is polished. Thesurface of the inter-layer insulation film 26 is thus planarized.

Then, as illustrated in FIG. 10B, with the silicon nitride film 24 asthe etching stopper, the contact holes 28 a-28 c are formed in theinter-layer insulation film 26 by photolithography. The contact holes 28a-28 c are formed in the inter-layer insulation film 26 by dry etching.The etchant gas is, e.g., a CF-based etching gas. The etching system is,e.g., a high density plasma etching system. The inter-layer insulationfilm 26 is etched with a high selectivity ratio to the silicon nitridefilm 24, whereby the silicon nitride film 24 can stop the etchingwithout failure.

Then, as illustrated in FIG. 11A, the silicon nitride film 24, etc.exposed in the contact holes 28 a-28 c are etched. The contact hole 28b, the contact hole 28 a and the contact hole 28 c are thus formedrespectively down to the upper electrode 20, the lower electrode 16 andthe gate electrode 20 a.

Next, the titanium film (not illustrated) and the titanium nitride film(not illustrated) are sequentially formed by, e.g., CVD. Thus, thebarrier metal film (not illustrated) of the titanium film and titaniumnitride film is formed. The film thickness of the titanium film is,e.g., about 10 nm. The film thickness of the titanium nitride film is,e.g., about 20 nm.

Next, a tungsten film is formed by, e.g., CVD. The film thickness of thetungsten film is, e.g., about 300 nm.

Then, the tungsten film and the barrier metal film are polished by,e.g., CMP until the surface of the inter-layer insulation film 26 isexposed. The conductor plugs 30 a-30 c of tungsten are thus buried inthe contact holes 28 a-28 c.

Thus, the semiconductor device according to the present embodiment isfabricated (see FIG. 11B).

The semiconductor device according to the present embodiment ischaracterized mainly in that, as described above, the transistor 40, andthe capacitor 32 according to the first embodiment are formed on one andthe same semiconductor substrate 10.

According to the present embodiment, the capacitor 32 has highreliability, accordingly the semiconductor device can have highreliability.

Modified Embodiments

The present invention is not limited to the above-described embodimentsand can cover other various modifications.

For example, in the above-described embodiments, the lower electrode isof N⁺ conduction type. However, the lower electrode is not essentiallyof N⁺ conduction type. For example, it is possible that an N type wellis formed in the device region 12, and a P⁺ type lower electrode isformed in the N type well.

1. A semiconductor device comprising: a device isolation region formedin a semiconductor substrate; a transistor including a gate insulationfilm formed of a thermal oxide film formed in a first device regiondefined by the device isolation region, and a gate electrode formed overthe gate insulation film and the device isolation region; a capacitorincluding a lower electrode formed in a second device region defined bythe device isolation region, a dielectric film formed over the lowerelectrode and formed of a thermal oxide film thicker than the gateinsulation film; and an upper electrode formed over the dielectric film;an insulation film formed over the semiconductor substrate, covering thetransistor and the capacitor; a first conductor plug buried in a firstcontact hole which is down to the lower electrode; a second conductorplug buried in a second contact hole which is down to the upperelectrode; and a third conductor plug buried in a third contact holewhich is down to the gate electrode, the upper electrode of thecapacitor being not formed over the device isolation region.
 2. Asemiconductor device according to claim 1, wherein a cavity is formed inthe device isolation region near the second device region.
 3. Asemiconductor device according to claim 1, wherein the device isolationregion is buried in a trench formed in the semiconductor substrate.
 4. Asemiconductor device according to claim 1, wherein a peak value of aimpurity concentration in the lower electrode is 1×10²⁰ cm⁻³ or more. 5.A semiconductor device according to claim 1, further comprising anetching stopper film formed below the insulation layer and havingetching characteristics different from those of the insulation layer. 6.A semiconductor device according to claim 1, wherein the semiconductorsubstrate is a silicon substrate, and the upper electrode is formed ofpolysilicon.
 7. A method for fabricating a capacitor comprising thesteps of: forming a device isolation region in a semiconductorsubstrate; forming a sacrifice oxidation film on the surface of thedevice region defined by the device isolation region; implanting animpurity in a region containing the device region to form a lowerelectrode of an impurity diffused layer: etching off the sacrificeoxidation film; forming a dielectric film on the surface of the impuritydiffused layer by thermal oxidation; forming an upper electrode over thedielectric film; forming an insulation layer, covering the upperelectrode; etching the insulation layer to form a first contact holedown to the lower electrode and a second contact hole down to the upperelectrode; and burying the first conductor plug in the first contacthole and burying the second conductor plug in the second contact hole,in the step of forming the upper electrode, the upper electrode is notformed over the device isolation region.
 8. A method for fabricating acapacitor according to claim 7, wherein the step of forming the deviceisolation region includes the step of forming a trench in thesemiconductor substrate, the step of forming another insulation layer inthe trench and over the semiconductor substrate, and the step ofpolishing said another insulation layer except in the trench to form thedevice isolation region of said another insulation layer.
 9. A methodfor fabricating a capacitor according to claim 7, wherein in the step offorming the lower electrode, the impurity is implanted with a peak valuethereof being 1×10²⁰ cm⁻³ or more.
 10. A method for fabricating acapacitor according to claim 7, which further comprises, after the stepof forming the upper electrode and before the step of forming theinsulation layer, the step of forming an etching stopper film havingetching characteristics different from those of the insulation layer,covering the upper electrode, and in which the step of forming the firstcontact hole and the second contact hole includes the step of etchingthe insulation layer at a high selectivity ratio to the etching stopperfilm to form the first contact hole and the second contact hole down tothe etching stopper film, and the step of etching off the etchingstopper film exposed in the first contact hole and the second contacthole to form the first contact hole down to the upper electrode and thesecond contact hole down to the lower electrode.
 11. A method forfabricating a semiconductor device comprising the steps of: forming adevice isolation region in a semiconductor substrate; forming asacrifice oxidation film on the surface of a device region defined bythe device isolation region and the surface of another device regiondefined by the device isolation region; implanting an impurity into aregion containing said another device region to form a lower electrodeof a impurity diffused layer; etching off the sacrifice oxidation film;forming a gate insulation film on the surface of the device region, anda dielectric film thicker than the gate insulation film on the surfaceof the impurity diffused layer, by thermal oxidation; forming a gateelectrode over the gate insulation film and the device isolation region,and an upper electrode over the dielectric film; forming an insulationlayer, covering the gate electrode and the upper electrode; etching theinsulation layer to form a first contact hole down to the lowerelectrode, a second contact hole down to the first electrode and a thirdcontact hole down to the gate electrode; and burying a first conductorplug, a second conductor plug and a third conductor plug respectively inthe first contact hole, the second contact hole and the third contacthole, in the step of forming the upper electrode, the upper electrodebeing not formed over the device isolation region.
 12. A method forfabricating a capacitor according to claim 11, wherein the step offorming the device isolation region includes the step of forming atrench in the semiconductor substrate, the step of forming anotherinsulation layer in the trench and over the semiconductor substrate, andthe step of polishing said another insulation layer except in the trenchto form the device isolation region of said another insulation layer.13. A method for fabricating a capacitor according to claim 11, whereinin the step of forming the lower electrode, the impurity is implantedwith a peak value thereof being 1×10²⁰ cm⁻³ or more.
 14. A method forfabricating a capacitor according to claim 11, which further comprises,after the step of forming the gate electrode and the upper electrode,and before the step of forming the insulation layer, the step of formingan etching stopper film having etching characteristics different fromthose of the insulation layer, covering the gate electrode and the upperelectrode, and in which the step of forming the first contact hole, thesecond contact hole and the third contact hole includes the step ofetching the insulation layer at a high selectivity ratio to the etchingstopper film to form the first contact hole, the second contact hole andthe third contact hole down to the etching stopper film, and the step ofetching off the etching stopper film exposed in the first contact hole,second contact hole and the third contact hole to form the first contacthole down to the upper electrode, the second contact hole down to thelower electrode and the third contact hole down to the gate electrode.